A 32-Bit Ripple-Ling Hybrid Carry Adder

This paper explores the design and implementation of a 32-bit Ripple-Ling Hybrid Carry Adder, aimed at optimizing the balance between hardware resource utilization and computational throughput. In wide-word arithmetic units, the carry propagation delay of high-order bits typically dominates the critical path. The proposed architecture addresses this by employing a non-uniform partitioning strategy: the low-order 11 bits are implemented using a Ripple Carry Adder (RCA) structure to minimize area and static power consumption, while the high-order 21 bits utilize a Ling-based parallel prefix tree. . The architecture was modeled in VHDL and evaluated using the Xilinx Vivado synthesis tool. Experimental data reveals a significant reduction in Look-Up Table (LUT) utilization compared to conventional ripple-carry architectures, demonstrating the effectiveness of the hybrid approach for resource-constrained digital systems. The results provide a comparative analysis of power consumption and area efficiency, establishing the Ripple-Ling hybrid adder as a viable candidate for energy-efficient arithmetic logic unit (ALU) design.