A 1.5-GS/s 12-bit 58.9-dB SNDR Pipelined ADC with Weight-Regulated Dither-Based Interstage Gain Error Calibration

This paper presents a novel weight-regulated, dither-based hybrid dual-stage background calibration technique for interstage gain errors (IGEs) in pipelined analog-to-digital converters (ADCs). To evaluate IGEs, a 1-bit pseudorandom dither is first injected into the first three stages. The proposed algorithm then evaluates IGEs via correlation. The first stage employs a large fixed-step Least Mean Squares (LMS) algorithm to rapidly estimate the gain error. The second stage utilizes the first stage’s output to suppress fluctuations using a weighted error and refines the estimate through a rational-quadratic adaptive-variable-step (RQ-AVS) LMS method. The proposed technique was verified using a fabricated 1.5-GS/s 12-bit pipelined ADC prototype implemented in a 28-nm CMOS process and featuring a 5.9-GHz input bandwidth. Measurement results show that at a 745 MHz input, the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) improve from 52.1 dB and 65.8 dBc to 58.9 dB and 74.3 dBc, respectively. During calibration, the algorithm converges within 0.12 million samples, reducing steady-state estimation variation from +10.93%/−12.51% to +1.29%/−2.13%. The ADC achieves +0.25/−0.24 LSB differential nonlinearity (DNL) and +0.80/−0.75 LSB integral nonlinearity (INL) with a power consumption of 102.4 mW.