A 10‐Bit 400‐MS/s Subrange SAR ADC With Binary‐Scaled Recombination Capacitive DAC in 28‐nm CMOS

ABSTRACT

This paper presents a 10‐bit 400‐MS/s subrange successive approximation register (SAR) analog‐to‐digital converter (ADC) designed in a 28‐nm process. To mitigate the gain errors inherent in the subrange SAR architecture, a binary‐scaled recombination redundancy algorithm is adopted. In addition, a detect‐and‐skip algorithm is designed to further enhance the conversion efficiency. An improved low‐noise comparator topology is also introduced. By adding an extra transistor, the variation of parasitic capacitance at the comparator input nodes during the ADC sampling phase is suppressed, which improves the ADC linearity. To validate the effectiveness, an ADC schematic is designed and simulated. The simulation results show that the ADC achieves a 61.95‐dB SFDR and 53.67‐dB SNDR at 196.9‐MHz input frequency.