A 0.9 V Low-Power Body-Biased StrongARM Latch Comparator with Reduced Kickback Noise for High-Speed Analog-to-Digital Converters

This paper describes a low-power body-biased StrongARM (SA) latch comparator with low kickback noise, under a supply of 0.9 V for high-speed analog-to-digital converter design applications. To improve the speed of the SA latch comparator, a novel low-power clocked forward body biasing (CFBB) technique based on the auxiliary transistor technique is proposed. Moreover, the proposed CFBB SA latch comparator is compared with the prior conventional CFBB and the improved CFBB SA latch comparators. This work is significant because circuits have been implemented with layouts using a triple-well process. Their parasitic extraction (PEX), post-layout simulation and pre-layout simulations are performed in 45-nm CMOS technology. The proposed CFBB exhibits the best power, delay, offset and kickback noise performance in both pre-layout and post-layout simulations. The proposed CFBB SA comparator achieves a power saving of 17% and a speed improvement of 24% compared with the improved CFBB SA latch comparator. In terms of kickback noise, the proposed CFBB gives only 19.22 [Formula: see text]A, which is 42% less than the improved CFBB SA latch comparator at 1 GHz frequency. Finally, for the proposed CFBB SA latch comparator, a Monte Carlo simulation is performed for 500 samples, which gives an input-referred offset of only 2.90 mV.