1um Multi-Layer High Density Build Up (HDBU) Substrates

In early 2024 American Semiconductor (ASI) demonstrated advanced Build-Up Substrate technology that was down selected as one of eight substrate technologies invited for CHIPS program consideration. Although ASI was not selected for CHIPS funding, ASI continued High Density Build-Up (HDBU) substrate development and commercialization. In 2024 ASI made extensive advancements in substrate harsh environment reliability testing capability in collaboration with ARL/FlexTech. In 2025 ASI advanced HDBU MRL with the support of DARPA. ASI’s advanced HDBU substrate is evolving with two primary metallization’s. Ultraflex™ Cu-on-PI is most applicable to advanced packaging. Nobleflex™ Au-on-PI is gaining adoption for medical device applications. Industry requirements for advanced substrates are driving minimum feature scaling to ≤1um and layer counts in excess of 30. Ultraflex/Nobleflex provide the first commercially available U.S. HDBU advanced substrates. Ultraflex/Nobleflex were first released in late 2025 with 1um minimum features and 2 layers that provided an immediate source for advanced HDBU substrates while proving out core capability necessary for smaller features and higher layer counts. This presentation will include a discussion of U.S. capabilities for advanced substrates, advanced substrate and board architectures, Ultraflex/Nobleflex technology demonstrators, Ultraflex/Nobleflex test results, and advanced substrate reliability characterization and results.  

ASI’s Ultraflex ASUF01-200 process is a maskless advanced substrate process optimized to support multi-layer capability for FOWLP, 2.5D, 3D and HI applications. The Ultraflex 1um copper process is currently in pilot production on 200mm substrates. Sept 2025 in-line Ultraflex metrology shows 1um features. On-substrate electrical test monitors show high fidelity M1 patterns after processing. Electrical testing yields anticipated values for the 1µm M1 serpentine at a median value of 50.72 Ohm actual vs 49.47 Ohm theoretical. 

ASI is extremely aware of the critical elements for commercialization: product, market, capacity.  HDBU substrates and their associated use in chiplet, SiP, 2.5D, 3D and HI applications are very new technology. The big question for new substrate capability is the level of market demand. This question is not just for ASI, but for HDBU in general. If emerging HDBU manufacturers like ASI cannot procure initial engagements to start scaling, the result will surely be that when the technology does start to deploy, it will be from off-shore sources profiting from American innovation. It is often noted that U.S. government procurement does not have the volume to influence commercial electronics. For mature applications this is true. However, low-to-mid volume high mix demand is precisely what is needed to develop new on-shore manufacturers. This type of demand allows new manufacturers to bridge the often lamented “valley-of-death” and can provide the on-ramp needed to catalyze new on-shore manufactures. To engage early market adoption, ASI is rolling out the MPS (Multi-Project Substrate) program. This program is to HDBU what multi-project-wafers are to wafer foundries. Customers can subscribe to a MPS run without having to contract an entire lot. ASI’s MPS program provides a unique new capability that supports advancement of all advanced packaging efforts that require fine-feature substrates.