Hardware architectures for computing the cosine transforms over the finite field F28$\mathbb {F}_{2^8}$

Abstract

This article presents hardware architectures for computing four types of the 8‐point cosine transforms over the finite field . The proposed architectures utilize three distinct approaches, described in SystemVerilog, and are synthesized on a field‐programmable gate array (FPGA) SoC platform. To implement the design, an improved version of a standard multiplier is presented by precomputing the required constants, thereby reducing hardware complexity. The system is integrated as a memory‐mapped Dual Core Cortex A9 peripheral to test the proposed architecture in the employed FPGA SoC. Among the three proposed architectures, one can choose to work up to 218.39 MHz, using 626 Logic Elements (LE) and 608 one‐bit registers; work up to 171 MHz, using 313 LE and 128 one‐bit registers; or work up to 197.36 MHz, at the cost of 350 LE and 293 one‐bit registers.